Name: 
 

CMT - Chapter 7



True/False
Indicate whether the statement is true or false.
 

 1. 

A fully buffered DIMM uses an advanced buffering technique that makes it possible for servers to support a large number of DIMMs.
 

 2. 

Newer DRAM memory types operate asynchronously.
 

 3. 

Synchronous memory retrieves data faster than asynchronous memory.
 

 4. 

ECC memory is more reliable than non-ECC memory.
 

 5. 

A parity error rarely causes the system to halt.
 

Multiple Choice
Identify the choice that best completes the statement or answers the question.
 

 6. 

SIMMs have a ____ data path.
a.
4-bit
c.
32-bit
b.
16-bit
d.
64-bit
 

 7. 

DIMM technologies have a ____ data path.
a.
4-bit
c.
32-bit
b.
16-bit
d.
64-bit
 

 8. 

____ EDO is a refined version of EDO.
a.
Burst
c.
Dual
b.
Flash
d.
Synchronous
 

 9. 

SDRAM has ____ notch(es).
a.
one
c.
three
b.
two
d.
four
 

 10. 

SDRAM uses ____ pins.
a.
64
c.
144
b.
112
d.
168
 

 11. 

DDR SDRAM has ____ notch(es).
a.
one
c.
three
b.
two
d.
four
 

 12. 

DDR SDRAM uses ____ pins.
a.
112
c.
184
b.
164
d.
240
 

 13. 

DDR2 SDRAM has a ____-pin DIMM.
a.
164
c.
240
b.
185
d.
356
 

 14. 

With ____, the memory controller can communicate with two DIMMs at the same time, effectively doubling the speed of memory access.
a.
dual registers
c.
dual channels
b.
serial registers
d.
serial channels
 

 15. 

If a slot does not hold a RIMM, it must hold a placeholder module called a ____ to ensure continuity throughout all slots.
a.
S-RIMM
c.
RIMM2
b.
C-RIMM
d.
RIMMX
 

 16. 

A ____ is an area on the motherboard that holds the minimum number of memory chips or memory modules that must work together as a unit.
a.
pool
c.
bank
b.
bundle
d.
farm
 

 17. 

The use of a parity bit means that every byte occupies ____ bit(s).
a.
one
c.
eight
b.
two
d.
nine
 

 18. 

Today’s memory uses a new method of error checking called ____ that can detect and correct an error in a single bit.
a.
CAS
c.
ECC
b.
RAS
d.
parity
 

 19. 

____ Latency and ____ Latency are two ways of measuring speed.
a.
BEDO, RAS
c.
BEDO, GPF
b.
CAS, RAS
d.
EDO, ECC
 

 20. 

SDRAM, DDR, DDR2, and RIMM are measured in ____.
a.
MHz
c.
CAS Latency
b.
PC rating
d.
RAS Latency
 

 21. 

A ____ is a measure of the total bandwidth of data moving between the module and the CPU.
a.
MHz
c.
CAS Latency
b.
PC rating
d.
RAS Latency
 

 22. 

On older motherboards, 30-pin SIMMs are installed in groups of ____.
a.
two
c.
four
b.
three
d.
five
 

 23. 

A DIMM slot can hold ____ bank(s).
a.
one
c.
three
b.
two
d.
four
 

 24. 

When looking at an advertisement for DIMMS, ____ of the module indicate(s) the width of the data bus.
a.
size
c.
density
b.
weight
d.
rings
 

 25. 

For RIMM modules, install the RIMMs beginning with bank ____.
a.
0
c.
2
b.
1
d.
3
 

 26. 

DDR2 SDRAM has a ____-bit data path.
a.
16
c.
64
b.
32
d.
128
 

Completion
Complete each statement.
 

 27. 

If a memory module doesn’t support registers or buffers, it is always referred to as a(n) ____________________ DIMM.
 

 

 28. 

____________________ refers to an error-checking procedure in which either every byte has an even number of ones or every byte has an odd number of ones.
 

 

 29. 

To upgrade memory means to add more ____________________ to a computer.
 

 

 30. 

Stamped on each chip of a RAM module is a(n) ____________________ that identifies the date the chip was manufactured.
 

 

 31. 

In Windows, memory errors can cause frequent ______________________________ errors.
 

 

Matching
 
 
Identify the letter of the choice that best matches the phrase or definition.
a.
DRAM
f.
C-RIMM
b.
SIMM
g.
DIMM
c.
PC rating
h.
EDO
d.
memory
i.
SDRAM
e.
concurrent RDRAM
 

 32. 

Temporarily holds data and instructions as the CPU processes them
 

 33. 

Always stored in either DIMM, RIMM, or SIMM modules
 

 34. 

Has independent pins on opposite sides of the module
 

 35. 

Has pins on both sides of the module; each pin pair is tied together into a single contact
 

 36. 

The first DIMM to run synchronized with the system clock
 

 37. 

An earlier version of Rambus memory
 

 38. 

A measure of the total bandwidth of data moving between the module and the CPU
 

 39. 

Refined version of FPM that speeds up access time
 

 40. 

A placeholder module; contains no memory chips
 



 
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